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Fuse test benchRaspberry PLC 19RGPIOSafety

Fail-safe interlocks for an automated test bench

Safety interlocks on a PLC are the difference between a lab toy and equipment people trust with 220 A. This example supervises three digital inputs on a Raspberry PLC 19R — a microfuse protection chain on I0.0, a normally-closed e-stop on I0.2 and the supply's end-of-test signal on I0.3 — and on any trip cuts the power source first, then latches the red beacon. The logic mirrors a real fuse test bench deployment.

Normally-closed everything

The e-stop and the microfuse chain are wired normally closed, so a cut cable, a loose terminal or a dead sensor reads exactly like a pressed button — the bench stops. Fail-safe means the failure mode of the wiring itself is a safe state, not a silent loss of protection.

Order of operations in a trip

The shutdown sequence is fixed: command the supply output off over SCPI, then switch the beacons via the PLC relays. Cutting power always comes first; signalling is cosmetic by comparison. The 100 ms supervision loop runs independently of the test logic, so a hung sequence cannot delay a trip.

Rearming without surprises

After a trip the code refuses to rearm until every input is back in its rest state — e-stop released, microfuse replaced, supply flag cleared. Only then does the red beacon clear. There is no auto-restart: the operator gets a clean, deliberate return to ready.

A snippet from the implementation

Straight from the example as deployed on the Raspberry PLC 19R — copy it freely:

def init_plc():
    rpiplc.init("RPIPLC_19R")
    for pin in (I_MICROFUSES, I_EMERGENCY_STOP, I_SUPPLY_TEST_END):
        rpiplc.pin_mode(pin, rpiplc.INPUT)
    for pin in (R_GREEN_BEACON, R_RED_BEACON):
        rpiplc.pin_mode(pin, rpiplc.OUTPUT)
        rpiplc.digital_write(pin, rpiplc.LOW)
View the full working example Get the full project pack

The full example is a complete program — wiring header, setup and main loop — ready to adapt to your application.

Frequently asked questions

Is a software interlock enough for a real machine?

It complements, never replaces, hardware protection. The bench keeps its hardwired e-stop contactor chain; the PLC layer adds fast supervision, diagnostics and a clean shutdown of the SCPI source.

Why monitor the supply's end-of-test output as an interlock?

The Sorensen XG asserts it when its internal test sequence ends or faults. Treating it like a trip means the PLC and the supply can never disagree about whether power should be flowing.

What does the rpiplc library add over plain GPIO?

It maps the industrial terminals of the Raspberry PLC (I0.x inputs, R0.x relays) to named calls like digital_read("I0.2"), handling the optocoupled 24 V input stages and relay drivers for you.

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